In this uncertain turbulent times of COVID-19 pandemic, Testonica Lab is proud to sponsor the 25th Anniversary IEEE European Test Symposium at the Gold level, thereby supporting the academic test community at large, including researchers, professors and PhD students. The industrial support money is contributed to lower participation fees for conference's general attendees, thereby increasing the participation as well as attractiveness and aliveness of the event.
Testonica's managing director Dr. Artur Jutman participated this week in the trade mission of the Minister of Foreign Trade and Information Technology Kaimar Karu to the Netherlands. The purpose of the visit of the Estonian Delegation was to strengthen bilateral relations between Estonia and European Space Agency (ESA), to introduce the Estonian Space Policy Program and Action Plan for 2020-2027.
Testing solder joints of BGA packages upon PCB assemblies is a challenging task unless X-Ray equipment is available. In numerous cases X-Ray (AXI) is too costly while functional test (FCT) and IEEE 1149.1 Boundary Scan (JTAG) cannot catch open defects in power or ground nets. During Nordic Test Forum (NTF'2019) conference in Tallinn this week, Testonica has presented a ground breaking technology capable to detect defects in Power Delivery Network (PDN) of FPGA-based products using no AXI.
26 February 2019, at embedded world exhibition in Nürnberg, ChipVORX-SI (Synthetic Instruments), a technology jointly developed by Testonica and GÖPEL electronic has received a prestigious embedded award in tools category. ChipVORX-SI allows configuring a test design for FPGAs easily and without developer knowledge - this convinced the jury of the embedded award 2019.
Testonica Lab has just signed a contract with EP-TeQ for the sales and distribution of its Quick Instruments solutions in the Nordic, Baltic and Benelux area. "Testonica has been a valued partner of ours already for several years, so it is also a pleasure for us that their Quick Instruments are now ready for distribution", says Director at EP-TeQ, Lars Kongsted-Jensen. "It is opening new doors to us that their embedded instrument IPs now can be used in a more open and flexible way".
Marginal Defects, such as excessive voids in solder joints, dewetting, head-in-pillow and alike do not necessarily cause malfunctions, but may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. As a result, Marginal Defects may lead to No Fault/Trouble Found (NFF/NTF) scenarios.
In its Aug-Sept issue, IEEE Instrumentation & Measurement Magazine published our technical paper that was originally presented last year at AUTOTESTCON conference in Anaheim, CA. It is one of six conference papers selected for the journal on a quality basis out of the total of 80 AUTOTESTCON'2016 contributions.
Testonica's director Dr. Artur Jutman serves this year as the General Chair of the 2nd International Test Standards Application Workshop (TESTA'2017). The TESTA workshop is a focused, open discussion platform dedicated to exchange of fresh ideas, industrial best practices, methodologies and work‐in‐progress around test related standards, especially those being actively developed today or the ones recently released.
In March 2015, work commenced on a European Union's Horizon 2020 Programme's collaborative research project H2020-ICT-2014-1-644905 IMMORTAL - Integrated Modelling, Fault Management, Verification and Reliable Design Environment for Cyber-Physical Systems. In frames of this project, a consortium of leading European academic and industrial players aim at combining their expertise in developing an integrated, cross-layer modeling based tool framework for fault management, verification and reliable design of dependable Cyber-Physical Systems (CPS).
Testonica offers several job positions related to HW and SW development primarily in two different categories: a) FPGA development using VHDL/Verilog, b) embedded SW development using C language. We are primarily looking for master students, but other candidates are welcome too.