Embedded Instrumentation

Testing solder joints of BGA packages upon PCB assemblies is a challenging task unless X-Ray equipment is available. In numerous cases X-Ray (AXI) is too costly while functional test (FCT) and IEEE 1149.1 Boundary Scan (JTAG) cannot catch open defects in power or ground nets. During Nordic Test Forum (NTF'2019) conference in Tallinn this week, Testonica has presented a ground breaking technology capable to detect defects in Power Delivery Network (PDN) of FPGA-based products using no AXI.

26 February 2019, at embedded world exhibition in Nürnberg, ChipVORX-SI (Synthetic Instruments), a technology jointly developed by Testonica and GÖPEL electronic has received a prestigious embedded award in tools category. ChipVORX-SI allows configuring a test design for FPGAs easily and without developer knowledge - this convinced the jury of the embedded award 2019.

Testonica Lab has just signed a contract with EP-TeQ for the sales and distribution of its Quick Instruments solutions in the Nordic, Baltic and Benelux area. "Testonica has been a valued partner of ours already for several years, so it is also a pleasure for us that their Quick Instruments are now ready for distribution", says Director at EP-TeQ, Lars Kongsted-Jensen. "It is opening new doors to us that their embedded instrument IPs now can be used in a more open and flexible way".

Marginal Defects, such as excessive voids in solder joints, dewetting, head-in-pillow and alike do not necessarily cause malfunctions, but may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. As a result, Marginal Defects may lead to No Fault/Trouble Found (NFF/NTF) scenarios.

In its Aug-Sept issue, IEEE Instrumentation & Measurement Magazine published our technical paper that was originally presented last year at AUTOTESTCON conference in Anaheim, CA. It is one of six conference papers selected for the journal on a quality basis out of the total of 80 AUTOTESTCON'2016 contributions.

Testonica's director Dr. Artur Jutman serves this year as the General Chair of the 2^nd International Test Standards Application Workshop (TESTA'2017). The TESTA workshop is a focused, open discussion platform dedicated to exchange of fresh ideas, industrial best practices, methodologies and work‐in‐progress around test related standards, especially those being actively developed today or the ones recently released.

The delivered solution enables quality evaluation of up to 10Gbit serial buses (PCIe Gen1/2/3, SATA, optical fiber channel, etc) with a help of powerful FPGA-embedded instrumentation technology. The technology is capable to measure Bit-Error Rate (BER) characteristic for high-speed digital data transmission links as well as to plot so-called BER eye diagram. The latter feature directly fits for mass-production testing since allows every manufactured product to be quickly checked for potential problems on high-speed channels.

Today, an average family spends over 50 Euros of hidden costs annually on No-Failure-Found (NFF) investigations - a known problem of an unknown origin. Tomorrow, the electronic engine control system in a car will be dying after three-five years of operation due to CMOS aging. Actions are urgently needed!

Testonica Lab has released universal virtual embedded instrument IP capable to measure frequencies of high-speed clock signals connected to FPGA device. The developed technology offers an easy way of checking frequencies of on-board oscillators without the need of using any kind of external test and measurement equipment. The method does not involve usage of external nail probes or any other means of physical access to oscillator’s pin.